Education / Logic
Logic Gate Simulator: Build and Test Digital Circuits
Drag AND, OR, NOT, NAND, NOR, XOR and XNOR gates onto a board. Connect switches, a clock and output LEDs, try example adders and an SR latch, and save your circuit as JSON.
Logic Gate Simulator: Build and Test Digital Circuits: Evaluates a circuit whenever its switches, clock or connections change. Unconnected pins show an unknown signal. The half adder and full adder demonstrate binary addition; the SR latch demonstrates feedback and memory. Feedback that does not settle is shown as unknown. The truth table treats each switch and clock as an independent input and starts each row from an all-low internal state. Runs 100% locally in your browser with zero server file uploads.
- Category
- School & study tools
- Runs
- In your browser
- Cost
- Free · no sign-up
- Availability
- Ready to use
Runs entirely in your browser
Drag a gate onto the board, or tap its button. Drag nodes to move them. Tap an output pin, then an input pin to draw a wire; dragging between pins also works. Tap an input switch to toggle it. Select a node to rename or remove it; arrow keys move a focused node.
Stable after 1 iterations. Unconnected pins show ?.
The SR latch uses two NOR gates. Set or reset establishes a state; both low retains the previous stable state. Both high is invalid. Releasing both together can oscillate in this simultaneous-update model. No analogue timing or propagation delay is simulated.
Wires: remove a connection
Circuit truth table
Inputs and clocks are independent variables, up to eight. Each row starts from an all-low internal state; feedback circuits can depend on history and have no single combinational truth table. ? marks unresolved or oscillating output.
| A | B | Sum | Carry | Settled |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Yes |
| 0 | 1 | 1 | 0 | Yes |
| 1 | 0 | 1 | 0 | Yes |
| 1 | 1 | 0 | 1 | Yes |
Digital logic
Gate definitions and combinational and sequential logic: MIT OpenCourseWare, Computation Structures, units 4 and 5. https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/ . Examples and diagrams on this page are original.
Simulation model
Signals are high, low or unknown. Updates occur simultaneously until the circuit settles, repeats a state or reaches 64 updates. This is a teaching model; it does not model electrical voltage, propagation delay or metastability. Feedback truth-table rows can depend on the initial state.
How to use it
- Drag gates onto the board or tap their buttons. Move a node by dragging it.
- Tap an output pin and then an input pin to connect them. Toggle input switches or run the clock.
- Inspect the live signals and truth table, or save and load the circuit locally or as a JSON file.
Privacy & limitations
The circuit runs in your browser. Local saves stay on this device; JSON exports are downloaded without uploading your circuit.
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Frequently asked questions
Why does an output show a question mark?
A required pin may be unconnected, or feedback may oscillate or fail to settle. The simulator stops after 64 simultaneous updates and shows unknown derived outputs rather than claiming a stable result.
How does the SR latch behave?
The example uses two NOR gates. Set or reset establishes a state, and both inputs low retains the previous stable state. Both inputs high is invalid; releasing both together can oscillate in this model. Analogue timing and propagation delays are not simulated.
What can I save?
JSON saves the nodes, labels, positions, switch settings and connections. It does not save the clock's running state or a latch's previous internal state. A local save uses this browser's storage; export and import let you move a circuit between devices.
How big can a circuit be?
The board accepts up to 80 nodes and 160 wires. The generated truth table supports up to eight input switches and clocks, giving at most 256 rows.
Free tool · runs in your browser · no account required